The invention relates to a circuit and method which provide thermal compensation for associated devices in a signal path in order to minimize shifts in offset voltages due to self-heating.
Conventional bipolar transistors operate approximately in accordance with the following equation: ##EQU1## where i.sub.c, i.sub.b, and i.sub.e are the collector, base, and emitter currents, respectively, i.sub.s is the saturation current for the transistor with predetermined geometry and doping, V.sub.BE is the base-emitter voltage, and q/kT is the reciprocal of the thermal voltage. Accordingly, solving for V.sub.BE results as follows: ##EQU2## where i.sub.s =i.sub.d e.sup.(-qEgo/kT), i.sub.d being a predetermined constant and E.sub.go being a constant approximately equal to 1.2V.
Substituting i.sub.s into equation (1) and simplifying results in the following: ##EQU3##
With respect to the above equations, it will be appreciated that for a given transistor, variances in temperature result in opposing changes in the base-emitter voltage. For example, for an increase in temperature in the transistor, the base-emitter voltage required to activate the transistor decreases. This relationship becomes critical when utilizing such transistors in matched pair configurations.
Matched pairs of transistors are commonly utilized as differential pairs in gain block circuits such as operational amplifiers and comparators, where a differential voltage is used as an input. The predetermined input offset voltage V.sub.os (the negative of the input voltage which must be applied across the input terminals of the pair in order to obtain zero output voltage) for such devices is ideally 0V, and in practice is a few millivolts. When the differential pair is used primarily for large signal operation, the small offset voltage is acceptable. When used in applications where a small input voltage represents some measured quantity as in a converter, meter, or measuring device, any nonzero input offset voltage can result in substantial error.
Offset voltage errors typically occur due to initial matching differences and to temperature drift in component parameters. Temperature drift refers to the change in input offset voltage resulting from change in temperature. The drift components may be compensated by introducing complementary temperature coefficients within the circuit. A common source of drift is local heating of diode junctions and resistive components having non-zero temperature coefficients.
Devices which are fabricated in dielectrically isolated processes exhibit much higher thermal resistances of individual devices than junction isolated processes, thus there is an even greater need for thermal compensation to prevent shifts in offset voltages due to self-heating. Full dielectric isolation is achieved by using silicon-on-silicon insulator wafers and trenching the silicon layer.
A cross-section of an exemplary NPN transistor 10 fabricated using an exemplary dielectrically isolated process is shown in FIG. 1. Initially, a silicon substrate 11 is subjected to an anisotropic etch which removes all the silicon in a specified area, and selectively stops at a buried silicon oxide layer 14 to form a trench 16. The trench is preferably 2 um wide and approximately 6 um deep. The trench 16 is then filled with polysilicon and oxide which eventually form a polysilicon barrier 18 and silicon dioxide barrier 20 to form a dielectrically isolated region 13 after doping.
The silicon substrate 11 consists of a p-type epitaxial layer which is counterdoped with a heavily doped n.sup.+ -type buried layer 22 and a lightly doped n-type diffusion 24 from the epitaxial layer surface (PNP devices are fabricated using p-type epitaxial layer with a heavily doped p.sup.+ -type buried layer). The upward diffusion of the buried layer 22 merges with the downward diffusion of the surface implant 24 and reverses the conductivity type of the epitaxial layer. The bases of the NPN and PNP (not shown) are formed by boron and phosphorus implants, respectively, or any desired p-type base diffusion 26. An extrinsic p-type base diffusion 28 is used to make an ohmic contact to the metallic base contact 27. A n-type diffusion 30, preferably arsenic, is implanted (boron for P-emitters) in the emitter material, preferably polysilicon. Deep contact diffusions 32 (plugs) are used for collector contacts in both NPN and PNP transistors. The collector plugs 32 help reduce collector (Rc) series resistance. An emitter diffusion 33 is also provided inside the plug and the extrinsic part of the bases to form ohmic contacts to these areas. Metallic contacts for the base 27, emitter 31, and collector 34 are formed using a conventional process.
Devices fabricated with such processes exhibit enhanced thermal isolation, and therefore are more susceptible to shifts in offset voltage due to self-heating during operation. Conventional methods for compensating for these self-heating effects include utilizing excessively large devices, degenerating and cascoding current mirrors, and running the transistors at lower currents. The use of excessively large devices have associated area and speed drawbacks. Degenerating and cascoding has a headroom disadvantage and can only be used with current mirrors, and not with differential pairs, to decrease self-heating effects. Operating transistors at lower currents has an associated device speed liability.